1. Field of the Invention
The present invention relates generally to switching systems, and more specifically to an asynchronous transfer mode multi-stage switching system with each stage being composed of basic switching blocks or modules.
2. Description of the Related Art
Self-routing switching systems have been proposed for switching high-speed asynchronous transfer mode (ATM) cells according to the destination address contained in their cell headers. Since cells of a given connection may take different routes of the system before arriving at the same destination depending on the traffic pattern, it is important to maintain cell sequence integrity for all cells of the connection. This is achieved by putting cells in a queue and waiting for an earlier cell when they arrive out of sequence. However, a total delay time of a cell transferred through the switching system would become substantial if out-of-sequence conditions occur in successive stages of the system.
To achieve low cell transfer delay a cell sequence control technique is described in an article "Design of a Multi-Stage Self-Routing Switch with a Distributed Cell Sequence Control", Hitoshi Obara, Japanese-language technical journal B-1, J72-B-1, No. 9, pages 698 to 709, the Institute of Electronics, Information and Communications Engineers of Japan. According to this known technique, a time stamp is attached to each incoming cell as it arrives at an entry point of a switching system and distributed evenly across the input links of a multi-stage self-routing network. When no cell exists at an entry point of the system, an idle cell containing a time stamp only is generated at that point and transferred to the self-routing network. Each stage of the system is composed of basic switching modules each consisting of N self-routing switches of (1.times.N) configuration and N groups of N first-in-first-out buffers, with the FIFO buffers being connected to respective outlets of the self-routing switches. N sequencers are associated with respective groups of the buffers to deliver cells to an output link of the switching module according to their time stamp values. When each self-routing switch receives an idle cell, it broadcasts its copies to all buffers.
However, buffer empty probability still exists in a switching module and this probability increases with the size of the switching module as well as with a biased traffic pattern of cells even if their arrival rates are uniform across all entry points of the system. Thus, the delay time reduction effect of the prior art switching system is degraded.